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[https://nvbugs/6646568][chore] Make DeepGEMM in-kernel barrier timeout configurable - #18179
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Included review availability: Your plan provides up to 12 included reviews per hour; 11 remain after this review. WalkthroughDeepGEMM barrier timeouts are now configurable through ChangesDeepGEMM barrier timeout
Estimated code review effort: 2 (Simple) | ~10 minutes Merge Risk: 🔵 Low · up to The change is mergeable with owner awareness: the configurable timeout is documented in seconds but relies on a fixed 2 GHz cycle conversion, so its effective wall-clock duration may vary across hardware or clock conditions. Sequence Diagram(s)sequenceDiagram
participant Environment
participant DeepGEMMJIT
participant DeviceBarriers
Environment->>DeepGEMMJIT: Set DG_JIT_BARRIER_TIMEOUT_SECONDS
DeepGEMMJIT->>DeviceBarriers: Compile DG_BARRIER_TIMEOUT_SECONDS
DeviceBarriers->>DeviceBarriers: Derive timeout cycles
DeviceBarriers-->>Environment: Report configured duration on timeout
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Inline comments:
In `@3rdparty/patches/deepgemm_configurable_barrier_timeout.patch`:
- Around line 41-42: Update the comment above kNumTimeoutCycles and the
referenced developer guide documentation to describe
DG_JIT_BARRIER_TIMEOUT_SECONDS as a nominal or approximate timeout, since the
fixed 2 GHz conversion may differ from the device’s clock64 rate across clock
settings and GPU generations.
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3rdparty/fetch_content.json3rdparty/patches/deepgemm_configurable_barrier_timeout.patchdocs/source/developer-guide/overview.md
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Approving — the comments below are optional touch-ups, not blockers.
Mechanically this is sound: I diffed the patch against the pinned DeepGEMM 8b1392b and all four hunks match (small line offsets only, which patch tolerates), the PATCH_COMMAND in 3rdparty/CMakeLists.txt runs before cpp/tensorrt_llm/deep_gemm stages the headers, and Compiler::build() does hash flags into kernel_signature, so the JIT-cache claim in the description holds. Both NVCCCompiler and NVRTCCompiler rebuild flags from the base string, so the -D survives on both paths, and the NVRTC whitespace split is fine since the flag has no spaces.
Two things to settle before merging:
- Has this gone to DeepGEMM upstream? The barrier budget is upstream's to own, and carrying a local patch means every pin bump can break the build (loudly, but still). A pointer to an upstream issue/PR in the patch header would let this be dropped at the next bump.
- The description says this does not fix 6646568 — worth confirming with the bug owner that a diagnostic-only knob is still wanted here rather than folded into the next DeepGEMM bump.
…ut configurable DeepGEMM's MegaMoE kernels synchronize expert-parallel ranks with in-kernel barriers that self-abort after a hard-coded 60s budget (`kNumTimeoutCycles` in `comm/barrier.cuh`). When the budget is exceeded the kernel trips a device-side assert, poisoning the CUDA context, so the surfaced traceback points at whatever kernel ran next rather than at the barrier — as seen on nvbugs/6646568, where a 16-rank GB300 context server died with `signal=8, target=16` and reported the failure from an unrelated FLA conv1d kernel. The budget is not tunable, which makes it impossible to tell a slow-but-healthy rendezvous from a genuine hang without editing installed third-party headers by hand. Note also that the DeepGEMM revision currently pinned here lowered this budget from 300s to 60s and added the same timeout to `grid_sync`, so builds that previously tolerated a slow first collective can now fail. Add `3rdparty/patches/deepgemm_configurable_barrier_timeout.patch`, wired in via the existing `patch_file` mechanism in `fetch_content.json`: - `comm/barrier.cuh`: derive `kNumTimeoutCycles` from a `DG_BARRIER_TIMEOUT_SECONDS` macro that still defaults to 60, and include the effective budget in both timeout diagnostics. - `csrc/jit/compiler.hpp`: translate the `DG_JIT_BARRIER_TIMEOUT_SECONDS` environment variable into `-DDG_BARRIER_TIMEOUT_SECONDS=<n>`. Because the JIT flags string is part of the kernel signature, changing the value recompiles the affected kernels instead of reusing a cached binary. Default behavior is unchanged: with the variable unset, or set to a non-positive value, kernels keep the upstream 60s budget. Also document the knob and how to read the barrier diagnostics in the developer guide overview. Signed-off-by: Jonas Li <6110159+longlee0622@users.noreply.github.com>
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…3: Make MoE communication timeouts follow the warmup phase Merge back the change of NVIDIA#19593 (release/1.3, f5eaf58) to main. MoE communication kernels that wait for peers inside the kernel trap once a peer is late by more than a device-side timeout. During warmup, one-time per-rank work such as JIT compilation and autotuning can delay a healthy rank by minutes, so a process-wide MoECommTimeoutGuard now relaxes those timeouts while the engine warms up and restores them for serving. NVLinkOneSided, DeepGEMM MegaMoE, DeepEP and NcclEP each register a MoECommTimeoutProxy. Only the CUDA-graph capture pass runs with the serving timeouts, because captured graphs keep their launch arguments. Adaptations to main: - Replace the NVLinkOneSided-only warmup budget of NVIDIA#19610 with the guard; TRTLLM_NVLINK_ONE_SIDED_A2A_[WARMUP_]TIMEOUT_SEC become deprecated aliases of TRTLLM_MOE_COMM_[WARMUP_]TIMEOUT_SEC, like TRTLLM_MOE_A2A_*. - Move the capture-pass switch into DecoderRunner after the runner refactor. - Re-author the DeepGEMM barrier-timeout patch for b64107f2. NVIDIA#19727 dropped the NVIDIA#18179 patch when it bumped DeepGEMM, so this also makes DG_JIT_BARRIER_TIMEOUT_SECONDS take effect again. - Let a fetch_content.json dependency list several patch files. Signed-off-by: xxi <xxi@nvidia.com>
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Summary
DG_JIT_BARRIER_TIMEOUT_SECONDS.-DDG_BARRIER_TIMEOUT_SECONDS=<n>.3rdparty/fetch_content.json.Dev Engineer Review
DG_JIT_BARRIER_TIMEOUT_SECONDSis unset or non-positive.QA Engineer Review
No test changes.
Description
Background. In nvbugs/6646568 a 16-rank GB300 Kimi-K3 FP4 disaggregated context server dies during KV-cache calibration. The surfaced traceback points at an unrelated FLA causal-conv1d kernel, but the actual first failure is DeepGEMM's in-kernel barrier:
signal=8, target=16— exactly half the expert-parallel group never arrived, 59s after all 16 ranks entered the calibration forward. The barrier'sDG_DEVICE_ASSERTpoisons the CUDA context, which is why the reported error comes from whatever kernel ran next.Problem. The barrier budget is a hard-coded 60s constant (
kNumTimeoutCyclesin the third-partydeep_gemm/comm/barrier.cuh). There is no way to tell a slow-but-healthy rendezvous from a genuine hang or a rank-count mismatch without hand-editing installed headers. Worth noting: the DeepGEMM revision currently pinned here (8b1392b) lowered this budget from 300s to 60s and added the same timeout togrid_sync, so setups that previously tolerated a slow first collective can now fail.Change. Add
3rdparty/patches/deepgemm_configurable_barrier_timeout.patch, wired in through the existingpatch_filemechanism in3rdparty/fetch_content.json(same mechanism already used for deep_ep, msa and xgrammar):deep_gemm/include/deep_gemm/comm/barrier.cuh— derivekNumTimeoutCyclesfrom aDG_BARRIER_TIMEOUT_SECONDSmacro that still defaults to 60, and include the effective budget in both timeout diagnostics (... timeout (60s): ...) so logs are self-describing.csrc/jit/compiler.hpp— translate theDG_JIT_BARRIER_TIMEOUT_SECONDSenvironment variable into-DDG_BARRIER_TIMEOUT_SECONDS=<n>. Because the JIT flags string is part of the kernel signature, changing the value recompiles the affected kernels instead of silently reusing a cached cubin.Also documents the knob and how to read the barrier diagnostics in
docs/source/developer-guide/overview.md.Risk. None by default. With the variable unset — or set to a non-positive value — kernels keep the upstream 60s budget. The only behavioral delta is the two diagnostic strings now carrying the effective budget.
Scope. This is a diagnostic enabler, not a fix for 6646568. It makes it possible to distinguish a slow rendezvous (all ranks eventually arrive) from a real desync (the same
signal/targetsplit reappears at a larger budget) without patching installed headers by hand.Test Coverage
No new automated tests: the change is confined to a third-party patch whose device half is JIT-compiled at runtime, so there is no unit-test surface in this repo. Verified manually on an 8xB200 host with the container image from
jenkins/current_image_tags.properties:Patch application — applies cleanly to a pristine
deepgemm-src(patch -p1 --dry-run+ real apply), and is idempotent: after application,patch -p1 --reverse --batch --dry-runsucceeds, so a CMake reconfigure takes the||branch instead of reporting an inconsistent patch state.Device half — standalone
nvcc -arch=sm_100acompile of a probe that instantiates bothgrid_syncandnvlink_barrier:kNumTimeoutCycles == 60 * 2e9— passes;-DDG_BARRIER_TIMEOUT_SECONDS=300asserts== 300 * 2e9— passes;-D...=300while asserting== 60) is correctly rejected by thestatic_assert.Host half — patched
csrc/jit/compiler.hppcompiles.CMake wiring, end to end — a clean out-of-tree build (
build_wheel.py --build_root ...,-a 100-real) completes and produces a wheel; the freshly re-fetcheddeepgemm-srcunder the new build root contains the patchedbarrier.cuhandcompiler.hpp, confirmingPATCH_COMMANDapplies on a pristine upstream clone rather than only by hand.Runtime plumbing — installed the resulting wheel and triggered a DeepGEMM JIT compile with
DG_JIT_PRINT_COMPILER_COMMAND=1, clearingDG_JIT_CACHE_DIRbetween runs:DG_JIT_BARRIER_TIMEOUT_SECONDS-DDG_BARRIER_TIMEOUT_SECONDS300-DDG_BARRIER_TIMEOUT_SECONDS=3000Still to be exercised on real hardware: the diagnostic string on an actual MegaMoE barrier timeout, which is the next step on 6646568 itself.
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